********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Sep 15, 2014
*ECN S14-1860, Rev. D
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SUP_SUB85N10-10 4 1 2
M1  3 1 2 2 NMOS W=11368080u L=0.50u 
M2  2 1 2 4 PMOS W=11368080u L=0.40u 
R1  4 3     RTEMP 70E-4
CGS 1 2     4100E-12
DBD 2 4     DBD
**************************************************************************
.MODEL  NMOS       NMOS  (LEVEL  = 3               TOX    = 7E-8
+ RS     = 6E-4           RD     = 0               NSUB   = 13.3E16  
+ KP     = 8.5E-6         UO     = 650             
+ VMAX   = 0              XJ     = 5E-7            KAPPA  = 20E-2
+ ETA    = 1E-4           TPG    = 1  
+ IS     = 0              LD     = 0                         
+ CGSO   = 0              CGDO   = 0               CGBO   = 0 
+ TLEV   = 1              BEX    = -1.5            TCV    = 5.9E-3
+ NFS    = 0.8E12         DELTA  = 0.1)
*************************************************************************
.MODEL  PMOS       PMOS (LEVEL   = 3               TOX    = 7E-8
+NSUB    = 8E15           TPG    = -1)   
*************************************************************************
.MODEL DBD D (CJO=2050E-12 VJ=0.38 M=0.35
+RS=0.1 FC=0.5 IS=1E-12 TT=3.8E-8 N=1 BV=75.5)
*************************************************************************
.MODEL RTEMP R (TC1=7E-3 TC2=5.5E-6)
*************************************************************************
.ENDS
 
